1 256mb/288mb: 16 meg x 16/18 rdram micron technology, inc., reserves the right to change products or specifications without notice. 256mrdram_2.p65 ? rev. 7/00 ?2000, micron technology, inc. 256mb/288mb: 16 meg x 16/18 rdram advance rdram ? part numbers clk freq. access part number organization 1 (mhz) time (ns) MT6V16M16f2-3m 512k x 16 x 32 300 53 MT6V16M16f2-3b 512k x 16 x 32 356 50 MT6V16M16f2-3c 512k x 16 x 32 356 45 MT6V16M16f2-4c 512k x 16 x 32 400 45 MT6V16M16f2-4d 512k x 16 x 32 400 40 mt6v16m18f2-3m 512k x 18 x 32 300 53 mt6v16m18f2-3b 512k x 18 x 32 356 50 mt6v16m18f2-3c 512k x 18 x 32 356 45 mt6v16m18f2-4c 512k x 18 x 32 400 45 mt6v16m18f2-4d 512k x 18 x 32 400 40 note : 1. the ?x32? designation indicates that this rdram core is comprised of 32 banks which use a ?split? bank architecture. MT6V16M16 - 512k x 16 x 32 banks mt6v16m18 - 512k x 18 x 32 banks for the latest data sheet, please refer to the micron web site: www.micronsemi.com/datasheets/datasheet.html rambus ? dram features ? high-speed 300 mhz, 356 mhz, and 400 mhz clocks with 2x data rates 1.6 gb/s peak i/o bandwidth rambus ? signaling level (rsl) using differential 300 mhz, 356 mhz, and 400 mhz transmit and receive clocks packet-oriented rambus protocol transmitted in 8-bit-long packets separate control (8-bit) and data (18-bit) buses for increased data bandwidth capability control bus with separate row (3-bit) and column (5-bit) buses for easier command scheduling programmable output delay timing for roundtrip delay of one to five cycles support for up to four simultaneous transactions (within bank restrictions) write buffer to reduce read latency three precharge mechanisms for controller flexibility programmable power states for flexibility in power consumption versus data access time power-down self-refresh and active refresh organization: 2kb pages and 32 banks, x16 or x18 fbga package interleaved data mode (idm) on the mt6v16m18 for system level error correction 32ms, 16,384 cycle refresh 2.5v power supply with 1.8v cmos supply for i/os options number configurations 16 meg x 16 16m16 16 meg x 18 16m18 package fbga f2 (84-pin, 2-row depopulated pinout) timing (cycle time) 300 mhz clock rate, access time = 53ns -3m 356 mhz clock rate, access time = 50ns -3b 356 mhz clock rate, access time = 45ns -3c 400 mhz clock rate, access time = 45ns -4c 400 mhz clock rate, access time = 40ns -4d part number example: MT6V16M16f2-3b 84-pin fbga (top view)
2 256mb/288mb: 16 meg x 16/18 rdram micron technology, inc., reserves the right to change products or specifications without notice. 256mrdram_2.p65 ? rev. 7/00 ?2000, micron technology, inc. 256mb/288mb: 16 meg x 16/18 rdram advance general description the MT6V16M16 rdram ? is a general-purpose, high-performance, packet-oriented, dynamic random- access memory containing 268,435,456, bits. the MT6V16M16 is internally configured as 32 banks of 64k x 128; each of the 64k x 128 banks is organized as 512 rows by 128 columns by 128 bits. the 128 bits are serially multiplexed onto the rdram?s i/o pins as eight 16-bit words. the mt6v16m18 rdram is a general-purpose, high- performance, packet-oriented, dynamic random- access memory containing 301,989,888 bits. the mt6v16m18 is internally configured as 32 banks of 64k x 144; each of the 64k x 144 banks is organized as 512 rows by 128 columns by 144 bits. the 144 bits are serially multiplexed onto the rdram?s i/o pins as eight 18-bit words. the MT6V16M16/mt6v16m18 use rambus signal- ing level (rsl) technology to achieve 300 mhz, 356 mhz or 400 mhz clock speeds using differential clocks. control and i/o data is transferred on both rising and falling edges of the clock. this allows data transfers at 1.25ns per two bytes (10ns per 16 bytes) during peak operation. all dram commands are communicated to the MT6V16M16/mt6v16m18 through a 3-bit row or 5-bit column bus in packets which are 8 bits in length. these packets are then decoded on the rdram into the operation and address requiring access. initialization and mode configuration for the MT6V16M16/mt6v16m18 are accessed through the slow-speed cmos serial i/o interface. the architecture of rdrams allows high sustained bandwidth memory transactions for multiple, simulta- neous, semi-random addresses. the rdram?s 32 banks can support up to four simultaneous transactions (within bank restrictions). system-oriented features include power manage- ment, byte masking, and x18 organization. the two data bits in the x18 organization are general and can be used for additional storage and bandwidth, or for error correction. additionally, the mt6v16m18 includes interleaved data mode (idm) which may be used to enable higher error correction algorithms at system level. device pinout the pinout tables below show the pin assignments of the center-bonded rdram package from the top side of the package (the view looking down on the package as it is mounted on the circuit board). the MT6V16M16 and mt6v16m18 devices are available in an fbga package with a ball pitch of 0.8mm. note : for the MT6V16M16 device, dqa8 and dqb8 are no connects. fbga package f2 pinout (top view) 10 v dd gnd v dd gnd v dd v dd v dd v dd gnd v dd 9 8 v dd cmd v dd gnd gnda gnda v dd v dd gnd gnd v dd v dd gnd gnd v cmos v dd 7 dqa8 dqa7 dqa5 dqa3 dqa1 ctmn ctm rq7 rq5 rq3 rq1 dqb1 dqb3 dqb5 dqb7 dqb8 6 5 4 gnd dqa6 dqa4 dqa2 dqa0 cfm cfmn rq6 rq4 rq2 rq0 dqb0 dqb2 dqb4 dqb6 gnd 3 gnd sck v cmos gnd v dd gnd v dd av ref gnd v dd gnd gnd v dd sio0 sio1 gnd 2 1 v dd gnd gnd v dd gnd gnd gnd gnd gnd v dd abcde fgh j klmnprs
3 256mb/288mb: 16 meg x 16/18 rdram micron technology, inc., reserves the right to change products or specifications without notice. 256mrdram_2.p65 ? rev. 7/00 ?2000, micron technology, inc. 256mb/288mb: 16 meg x 16/18 rdram advance dqa8..dqa0 dqb8..dqb0 18 5 3 row2..row0 col4..col0 ctm ctmn 2 sck,cmd rclk tclk control registers mb 8 8 7 5 5 5 5 5 6 9 5 5 11 devid refr rd, wr 18 18 2 sio0,sio1 rclk rclk rq7..rq5 or rq4..rq0 or xop decode prex prec c ma xop m dx bx cop s dc bc prer act rop av dr br r rclk tclk 18 18 18 packet decode colx colc colm 1:8 demux packet decode rowa rowr power modes mux row decode match dm match match column decode & mask write buffer mux mux 1:8 demux 144 internal data path bank31 i/o gating 18,432 bank0 memory array 512 rows x128 columns x144 bits sense amps 1:8 demux 8:1 mux write buffer cfm cfmn functional block diagram note : 1. the drawing is for the mt6v16m18 device. the MT6V16M16 device has a 128-bit internal bus width (instead of 144) and dqa8/dqb8 are not used. 2. function block diagrams illustrate simplified device operation.
4 256mb/288mb: 16 meg x 16/18 rdram micron technology, inc., reserves the right to change products or specifications without notice. 256mrdram_2.p65 ? rev. 7/00 ?2000, micron technology, inc. 256mb/288mb: 16 meg x 16/18 rdram advance table 1 cross reference for abbreviated device marks clk freq. access sample production part number (mhz) time (ns) marking marking MT6V16M16f2-3m 300 53 d7hdz dkhdz MT6V16M16f2-3b 356 50 d7hdy dkhdy MT6V16M16f2-3c 356 45 d7hdx dkhdx MT6V16M16f2-4c 400 45 d7hdv dkhdv MT6V16M16f2-4d 400 40 d7hdt dkhdt mt6v16m18f2-3m 300 53 d7jfz dkjfz mt6v16m18f2-3b 356 50 d7jfy dkjfy mt6v16m18f2-3c 356 45 d7jfx dkjfx mt6v16m18f2-4c 400 45 d7jfv dkjfv mt6v16m18f2-4d 400 40 d7jft dkjft device marking due to the size of the package, micron?s standard part number is not printed on the top of each device. instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used (see figure 1). the abbreviated device marks are cross referenced to the micron part numbers in table 1. d7kfw speed grade z = -3m y = -3b x = -3c v = -4c t = -4d number of dq pins d = 16 dq standard pinout f = 18 dq standard pinout device density h = 256mb j = 288mb product type 7 = rdram engineering sample device (84-pin, 2-row depopulated pinout) k = rdram production device (84-pin, 2-row depopulated pinout) product group d = dram figure 1 abbreviated device mark 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micronsemi.com, internet: http://www.micronsemi.com, customer comment line: 800-932-4992 micron is a registered trademark of micron technology, inc.
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